SK Hynix: The Memory Bottleneck Powering the AI Economy
Part 3 of The Hidden AI Winners Series
Disclaimer: This report is for informational purposes only and does not constitute investment advice, a recommendation, or a solicitation to buy or sell any security. All data is sourced from public filings, earnings releases, and third-party research as of February 28, 2026. Past performance is not indicative of future results. Investing in early-stage companies carries substantial risk of loss.
Executive Summary
SK Hynix (KRX: 000660) has emerged as the dominant supplier of the single most constrained component in AI infrastructure: High Bandwidth Memory. While investor attention has concentrated on GPU designers and hyperscaler capex, the memory subsystem has quietly become the binding constraint on AI accelerator performance — and SK Hynix controls approximately 57–62% of the global HBM market.
The company’s full-year 2025 results were transformational. Revenue reached 97.1 trillion won (~$67.9 billion), up 47% year-over-year. Operating profit surged 101% to 47.2 trillion won, with an operating margin of 49% for the year — expanding to 58% in Q4 2025. HBM revenue more than doubled year-over-year, accounting for approximately 40% of total DRAM sales by Q3 2025. The company exited 2025 as a net cash business with 34.9 trillion won in cash and equivalents.
The thesis is structural: every AI accelerator shipped — whether NVIDIA’s Blackwell, AMD’s Instinct, Google’s TPU, or Amazon’s Trainium — requires multiple stacks of HBM. The content per chip is increasing with each generation. Supply is fully allocated through 2026, with tightness extending into 2027. And HBM commands substantially higher margins than conventional DRAM, transforming what was historically a commodity business into a differentiated, supply-constrained profit pool.
This article examines whether HBM represents a temporary memory cycle — or a structural profit pool created by the AI revolution.
Coming Next in The Hidden AI Winners Series
The Hidden AI Winners series continues to map the critical infrastructure layers of the AI economy. Having examined power and cooling (Part 1: Vertiv), networking and custom silicon (Part 2: Broadcom), and memory bandwidth (Part 3: SK Hynix), the series will turn to the remaining structural bottlenecks enabling the AI buildout.
Key Takeaways for SK Hynix
Investment Highlights
SK Hynix holds 57–62% of the global HBM market, with first-mover advantage in HBM3E mass production and a roadmap to simultaneously supply HBM3E and HBM4 — a capability no competitor currently matches.
HBM revenue more than doubled year-over-year in 2025, reaching an estimated 40% of total DRAM revenue. HBM commands significantly higher margins than conventional DRAM, driving the company’s operating margin from 35% in FY2024 to 49% in FY2025.
The global HBM market is projected to grow from approximately $38 billion in 2025 to $58 billion in 2026, with a path toward $100 billion by 2028 — driven by increasing HBM content per AI accelerator and expanding deployment volumes.
HBM capacity for 2025 and 2026 is fully booked. Samsung and SK Hynix have reportedly negotiated 20% price increases on HBM3E contracts for 2026. Supply tightness may extend into 2027.
SK Hynix’s financial transformation is profound: operating margins expanded from a loss position in 2023 to 49% in 2025. The company transitioned to a net cash position with 34.9 trillion won in cash, up from 14.2 trillion won at year-end 2024.
At a market capitalization of approximately $433 billion and a trailing P/E of ~17x, the stock is priced below multiple semiconductor peers — though memory cyclicality and competitive risks warrant careful scenario analysis.
Where SK Hynix Fits in the AI Infrastructure Stack
To understand SK Hynix’s role in the AI economy, it is necessary to map the full infrastructure stack required to train and deploy large-scale AI models. Each layer represents a distinct engineering challenge, a distinct competitive landscape, and — critically — a distinct profit pool.
Parts 1 and 2 of this series examined the power and cooling layer (Vertiv) and the networking and custom silicon layer (Broadcom). Part 3 addresses what may be the most acutely constrained layer of all: memory bandwidth.
The fundamental challenge is this: AI accelerators can perform trillions of operations per second, but they can only process data as fast as memory can deliver it. In large language model inference, the model’s parameters must be continuously streamed from memory to the compute units. In training, massive gradient updates must flow between memory and processors at every step. If memory bandwidth cannot keep pace with compute throughput, the accelerator sits idle — and hundreds of thousands of dollars of silicon underperform.
This is the “memory wall” — and it has become the primary bottleneck in scaling AI systems. High Bandwidth Memory was engineered specifically to break through it.
The HBM Revolution
High Bandwidth Memory is a fundamentally different approach to connecting memory and processors. Rather than placing DRAM chips on a circuit board alongside the processor — as in traditional DDR or GDDR architectures — HBM stacks multiple DRAM dies vertically and connects them to the processor through thousands of microscopic copper pillars called through-silicon vias (TSVs).
How HBM Works
A single HBM stack consists of 8 to 16 DRAM dies bonded on top of a logic base die using advanced 2.5D packaging. The base die provides the interface to the processor, while the stacked dies provide capacity. TSVs create vertical electrical connections through the silicon itself, enabling a vastly wider data bus — 1,024 bits in HBM3E, compared to 64 bits for a single DDR5 channel — in a fraction of the physical footprint.
The result is a memory technology that delivers an order-of-magnitude more bandwidth per watt and per square millimeter than any conventional alternative. This is not an incremental improvement. It is an architectural discontinuity.
The bandwidth advantage of HBM is not marginal — it is an 18x improvement over DDR5 at the stack level, and a modern GPU like NVIDIA’s B200 uses six stacks of HBM3E, delivering over 8 TB/s of aggregate bandwidth. This is why every major AI accelerator designed since 2023 uses HBM, and why demand has structurally outstripped supply.
HBM Market Structure
The HBM market is an oligopoly. Only three companies in the world can manufacture it: SK Hynix, Samsung Electronics, and Micron Technology. The barriers to entry are extreme — HBM production requires advanced DRAM fabrication, TSV processing, die stacking and bonding capabilities, and integration with advanced 2.5D packaging provided by foundries like TSMC (CoWoS). No new entrant has emerged in over a decade, and none is expected.
Market Share: SK Hynix Dominates
SK Hynix has consistently held the leading position in HBM, driven by its early investment in TSV technology and its close co-development relationship with NVIDIA. In Q2 2025, SK Hynix held an estimated 62% of the HBM market by revenue, with Micron at 21% and Samsung at 17%. By Q3 2025, Samsung regained some ground — reaching 22% as its HBM3E parts were qualified by major customers — while SK Hynix held 57% and Micron remained at 21%.
SK Hynix's dominance is not accidental. The company was the first to achieve volume production of HBM3E, the current generation used in NVIDIA's H200 and B200 accelerators. It is also the only company positioned to simultaneously supply both HBM3E and HBM4 in volume during the 2026 transition period — a critical capability as customers require continuity of supply across product generations.
The demand drivers are compounding. Each new generation of AI accelerator requires more HBM stacks per chip. Google’s seventh-generation TPU integrates eight HBM3E stacks. Amazon’s Trainium3 uses four stacks. NVIDIA’s next-generation Rubin architecture is expected to increase HBM content further. Simultaneously, the total number of accelerators being deployed is growing exponentially as hyperscalers race to build AI capacity. The result is a demand curve that is growing at approximately 40% annually — significantly faster than the industry’s ability to expand supply.
SK Hynix’s Business Model
SK Hynix is the world’s second-largest memory semiconductor company by revenue, behind Samsung Electronics. The company operates primarily in two product segments: DRAM (including HBM) and NAND flash memory. The AI-driven demand for HBM is fundamentally reshaping the company’s revenue mix toward higher-margin, higher-value products.
Revenue Composition
The economic significance of this shift cannot be overstated. HBM commands a substantial price premium over conventional DRAM. A single HBM3E stack is priced at multiples of an equivalent-capacity DDR5 module, reflecting both the advanced manufacturing required (TSV processing, die stacking, rigorous testing) and the severe supply constraint. When HBM accounted for a small fraction of revenue, this premium was a curiosity. At 30%+ of revenue and growing, it is transforming the company’s profitability profile.
The HBM Economics: HBM production consumes approximately 18–28% of total DRAM wafer capacity across the three major memory makers, but accounts for a disproportionate share of revenue and profit. Each HBM stack requires 8–16 DRAM dies, plus a logic base die, processed through TSV and bonding steps. This diverts supply from conventional DRAM — tightening the broader market and supporting pricing power across the entire product portfolio.
