TSMC at the Center of the AI Boom: Strong Q3 Execution, Advanced Nodes, and Packaging Constraints
Taiwan Semiconductor Manufacturing Co. (TSMC) delivered a robust third-quarter 2025 performance, driven by surging demand for leading-edge AI and high-performance computing (HPC) chips. Consolidated revenue was NT$989.92 billion (US$33.10 billion), up 30.3% year-over-year and 6.0% sequentiallyinvestor.tsmc.com. Net income reached NT$452.30 billion, yielding diluted EPS of NT$17.44 – increases of 39.1% and 39.0% YoY respectivelyinvestor.tsmc.com. Gross margin improved to 59.5% (up 0.9 percentage point QoQ)investor.tsmc.com. For context, TSMC’s CFO noted that Q3 shipments of 3 nm, 5 nm and 7 nm wafers represented 23%, 37% and 14% of wafer revenue (with ≥7 nm advanced nodes at 74% of wafer sales). Management attributed the stronger margins and profits to higher capacity utilization and cost efficiencies at its fabs. Importantly, TSMC’s leadership in advanced processes and the AI/data-center cycle lifted key end markets: HPC (largely AI/data-center) accounted for 57% of revenue, smartphones 30%, with growth in IoT and automotive segments as well. Looking ahead, TSMC guided Q4’25 revenue of US$32.2–33.4 billion (implying roughly flat sequential USD growth, +22% YoY) and gross margin around 60%.
TSMC Business Model
TSMC pioneered the pure-play foundry model and remains the world’s largest dedicated contract chipmaker. It sells manufacturing services, not proprietary ICs, enabling hundreds of fabless companies and IDMs to outsource chip production. In 2024 TSMC operated 288 distinct process nodes and made 11,878 products for 522 customers. Its broad technology portfolio spans bleeding-edge logic (2 nm to 7 nm and beyond), specialty technologies (analog, RF, 22–40 nm) and advanced packaging (2.5D/3D packaging services). This mix lets TSMC serve many end markets – from smartphones to data centers to automotive – without being dependent on a single customer or segment. TSMC emphasizes scale and cost efficiency: it continually invests in new fabs and higher wafer volume, betting that higher output yields lower per-chip cost. The company also promotes its “foundry 2.0” concept – a vision of serving as a full-stack partner on chip design and packaging – which underlies its continued R&D and packaging investments. In sum, TSMC’s model rests on technology leadership (to attract cutting-edge chips) and a capital-intensive manufacturing base (to handle huge volumes), with a disciplined capital allocation to prioritize long-term growth. This strategy underpins management’s confidence in maintaining profit margins even as new fabs come online.
Financial Performance
TSMC’s Q3 financial results beat expectations in all key metrics. Revenue of NT$989.92 billion (US$33.10 billion) rose 30.3% YoY (from NT$759.69 billion in Q3’24) and 6.0% QoQinvestor.tsmc.com. Net income was NT$452.30 billion (+39.1% YoY)investor.tsmc.com. Diluted EPS came to NT$17.44, a 39.0% YoY jumpinvestor.tsmc.com. Margins were strong: gross margin was 59.5% (versus 58.6% in Q2’25 and 57.8% in Q3’24)investor.tsmc.com, and operating margin 50.6% (up ~1pp QoQ). Higher utilization and efficiency gains in TSMC’s fabs drove these margin improvements, offsetting some FX headwinds and costs of its overseas expansions. The net profit margin thus climbed to 45.7% (up about 3pp QoQ)investor.tsmc.com. Return on equity reached 37.8% (annualized)investor.tsmc.com, reflecting the capital-light foundry model and strong profitability.
On a U.S. dollar basis, revenue was US$33.10 billion, up 40.8% YoY and 10.1% QoQinvestor.tsmc.com. The weaker NT dollar (TWD ~29.91/$) helped reported NT$ growth, but management also cited robust demand as the core driver. In fact, TSMC’s Q3 results exceeded its own guidance: revenue and EPS beat forecasts, and gross margin overshot the high end by ~200 basis points, due primarily to FX and cost improvements. Free cash flow remained ample: the company generated TWD 427 billion from operations and spent TWD 287 billion on capex in Q3, ending the quarter with ~TWD 2.8 trillion in cash and securities (about US$90 billion). TSMC also continued its record dividend payouts: NT$117 billion was distributed for Q4’24 dividends, reflecting management’s commitment to a steadily growing cash dividend policy.
Overall, the financial drivers for the quarter were clear: leading-edge chip demand (AI/datacenter, smartphone logic) propelled revenue, while efficient operations and currency moves bolstered margins. CFO Wendell Huang emphasized that cost-improvement efforts and very high fab utilization (especially at 3nm/5nm lines) lifted margins to a near-cycle high, even as new fabs in the U.S. and Japan still dilute margins modestly.
Technology & Capacity Update
TSMC’s technology roadmap and capacity build-out remain on track for its long-term leadership. Node mix and ramp: In Q3, 3nm process accounted for 23% of wafer revenue, 5nm 37%, and 7nm 14%. In total, 74% of wafer revenue came from 7nm and below, underscoring TSMC’s focus on cutting-edge nodes. By contrast, mature nodes (16/20nm, 28nm, etc.) made up the remainder. TSMC is rapidly ramping its 3nm capacity to meet AI/GPU demand; management expects further growth in 3nm shipments in coming quarters. Meanwhile, production on 5nm (already a large volume node) and legacy 7nm remains steady for consumer and automotive chips. Looking ahead, TSMC reaffirmed its 2nm (“N2”) roadmap: the first N2 (and derivative N2P) production is on track for late 2025 and 2026, with A16 (an HPC-optimized variant with Super Power Rail) volume in 2H’26. Management said N2 will support both smartphone and HPC applications, and even introduced N2P and A16 to extend the N2 family’s performance. Indeed, TSMC described N2/N2P/A16 as a “large and long-lasting node” (i.e. another major inflection).
Advanced packaging continues to be a major focus and constraint. TSMC’s CoWoS (chip-on-wafer-on-substrate) 2.5D packaging is in high demand for AI accelerators and high-bandwidth designs. CEO C.C. Wei acknowledged that packaging capacity is “very tight” and that TSMC is “working very hard to narrow the gap” between demand and supply. Deloitte analysts note that CoWoS capacity is projected to double from ~35,000 wafers/month in 2024 to 70,000 by end-2025 (and grow further into 2026)deloitte.com. TSMC is expanding its packaging fabs accordingly. In fact, CFO Huang noted in the call that roughly 10–20% of capex in 2025 will go into advanced packaging/test facilities, reflecting this strategic priority. TSMC has also announced two dedicated packaging plants in Arizona to augment capacity (in addition to wafer fabs). The packaging build-out is a critical part of the capital plan given the industry-wide bottleneck.
